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-- Company: 
-- Engineer:
--
-- Create Date:   16:01:36 05/06/2011
-- Design Name:   ram
-- Module Name:   C:/Documents and Settings/Usuario/Mis documentos/Uni/Quinto/AIC/proyecto-manhattan-2/arquitectura/Interfaz/data/interfaz_mem/ram_tb.vhd
-- Project Name:  interfaz_mem
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: ram
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY ram_tb_vhd IS
END ram_tb_vhd;

ARCHITECTURE behavior OF ram_tb_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT ram
	PORT(
		addr : IN std_logic_vector(7 downto 0);
		d_in : IN std_logic_vector(7 downto 0);
		write_mode : IN std_logic;          
		d_out : OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL write_mode :  std_logic := '0';
	SIGNAL addr :  std_logic_vector(7 downto 0) := (others=>'0');
	SIGNAL d_in :  std_logic_vector(7 downto 0) := (others=>'0');

	--Outputs
	SIGNAL d_out :  std_logic_vector(7 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: ram PORT MAP(
		addr => addr,
		d_in => d_in,
		write_mode => write_mode,
		d_out => d_out
	);

	tb : PROCESS
	BEGIN

		-- Wait 100 ns for global reset to finish
		wait for 100 ns;
		d_in <= "00001111";
		write_mode <= '1'
		addr <= "00000001";
		-- Place stimulus here

		wait; -- will wait forever
	END PROCESS;

END;
